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? 2009 semtech corporation power management 1 SC195 3.5mhz, 500ma synchronous step down dc-dc regulator features input voltage 2.9v to 5.5v output voltage 0.8v to 3.3v output current capability 500ma effi ciency up to 94% 15 programmable output voltages high light-load effi ciency via automatic psave mode fast transient response temperature range -40 to +85c oscillator frequency 3.5mhz 100% duty cycle capability quiescent current 38a typ shutdown current 0.1a typ internal soft-start over-voltage protection current limit and short circuit protection over-temperature protection under-voltage lockout floating control pin protection mlpq-ut8 1.5 x 1.5 x 0.6 (mm) package pb free, halogen free, and rohs/weee compliant applications smart phones and cellular phones mp3/personal media players personal navigation devices digital cameras single li-ion cell or 3 nimh/nicd cell devices devices with 3.3v or 5v internal power rails ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? description the SC195 is a high effi ciency, 500ma step down regula- tor designed to operate with an input voltage range of 2.9v to 5.5 v. four control logic pins are used to select the output voltage, eliminating the need for external feed- back resistors. the control pins allow the output voltage to be set to a single level or controlled dynamically. fifteen diff erent output voltages can be selected. pulling all four control pins low disables the output. the SC195 operates at a fixed 3.5mhz switching fre- quency, minimizing the size and cost of external components. a power-save (psave) mode is used to opti- mize efficiency at light loads for each output setting. hysteresis is included to prevent chattering between psave and normal pulse-width modulation (pwm) mode. the SC195 provides short-circuit and thermal protection to safeguard the device under extreme operating condi- tions. other features include internal soft-start circuitry, limiting in-rush current, and under-voltage lockout, pre- venting the device from malfunction when the input voltage drops below the rated minimum level. these fea- tures coupled with the tiny 1.5x1.5x0.6 (mm) package make the SC195 a versatile product well suited for porta- ble applications. SC195 in ctl3 ctl2 ctl1 ctl0 lx out gnd v out 0.8v to 3.3v v in 2.9v to 5.5v l x 1.0 h c out 10 f c in 4.7 f control logic lines typical application circuit september 23, 2009
SC195 2 pin confi guration marking information ordering information device package SC195ultrt (1)(2) mlpq-ut8 1.5x1.5 SC195evb evaluation board notes: (1) available in tape and reel only. a reel contains 3,000 devices. (2) pb free, halogen free, and rohs/weee compliant top view ctl3 out in 7 lx 6 4 gnd 5 8 2 ctl1 1 ctl2 3 ctl0 0j yw mlpq-ut8; 1.5x1.5, 8 lead ja = 116c/w table 1 C output voltage settings ctl3 ctl2 ctl1 ctl0 vout 0 0 0 0 shutdown 0 0 0 1 0.80 0 0 1 0 1.00 0 0 1 1 1.20 0 1 0 0 1.40 0 1 0 1 1.50 0 1 1 0 1.60 0 1 1 1 1.80 1 0 0 0 1.85 1 0 0 1 1.90 1 0 1 0 2.00 1 0 1 1 2.20 1 1 0 0 2.50 1 1 0 1 2.80 1 1 1 0 3.00 1 1 1 1 3.30 0j = SC195 yw = date code
SC195 3 exceeding the above specifi cations may result in permanent damage to the devic e or device malfunction. operation outside of the parameters specifi ed in the electrical characteristics section is not recommended. notes: (1) tested according to jedec standard jesd22-a114. (2) calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer fr4 pcb with thermal vias under the exposed pad per jesd51 standards. absolute maximum ratings in (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 lx voltage (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0 to v in +0.5 other pins (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to v in + 0.3 output short circuit to gnd . . . . . . . . . . . . . . . . con tinuous esd protection level (1) (kv) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 recommended operating conditions input voltage range (v) . . . . . . . . . . . . . . . . . . . . . +2.9 to +5.5 operating temperature range (c) . . . . . . . . . . -40 to +85 thermal information thermal resistance, junction to ambient (2) (c/w) . . . . 116 junction temperature range (c) . . . . . . . . . . . -40 to +150 storage temperature range (c) . . . . . . . . . . . . -65 to +150 unless otherwise specifi ed: v in = 3.6v, c in = 4.7f, c out =10f, l x =1h, v out =1.8v, t j(max) =125c, t a = -40 to +85 c. typical values are t a =+25 c parameter symbol condition min typ max units output voltage range v out 0.8 3.3 (1) v output voltage tolerance v out_tol i out = 200ma -2.0 2.0 % psave mode 1.5 line regulation v linereg 2.9 v in 5.5v, i out = 200ma 0.3 %/v load regulation v loadreg 200ma i out 500ma -1 %/a average output current i out 500 ma current limit threshold i limit 800 1300 ma foldback current limit i fb_lim i load > i limit 150 ma under-voltage lockout v uvlo rising v in 2.9 v hysteresis 200 mv quiescent current i q no switching, i out = 0ma 38 60 a shutdown current i sd v ctl 0-3 = 0v 0.1 1.0 a lx leakage current i lx into lx pin 0.1 1.0 a high side switch resistance r dson_p i out = 100ma 250 m low side switch resistance r dson_n i out = 100ma 350 electrical characteristics
SC195 4 parameter symbol condition min typ max units switching frequency f sw 2.8 3.5 4.2 mhz soft-start t ss v out = 90% of fi nal value 100 500 s thermal shutdown t ot rising temperature 160 c thermal shutdown hysteresis t hyst 20 c logic inputs - ctl0, ctl1, ctl2, and ctl3 input high voltage v ih 1.2 v input low voltage v il 0.4 v input high current i ih v ctl 0-3 = v in -2.0 5.0 a input low current i il v ctl 0-3 = gnd -2.0 2.0 a notes (1) maximum output voltage is limited to vin if the input is less than 3.3v. electrical characteristics (continued)
SC195 5 typical characteristics effi ciency vs. i out (t a = -40c) 0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1000 load current (ma) efficiency (%) 3.3v 2.8v 1.8v 1v effi ciency vs. i out (t a = 25c) 0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1000 load current (ma) efficiency (%) 3.3v 1v 2.8v 1.8v effi ciency vs. i out (t a = 85c) 0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1000 load current (ma) efficiency (%) 1v 3.3v 2.8v 1.8v v out (v) efficiency (%) 65 70 75 80 85 90 95 100 0.5 1 1.5 2 2.5 33.5 4.2v 5.0v 3.6v i out = 200ma v out (v) efficiency (%) 4.2v 5.0v 3.6v 65 70 75 80 85 90 95 0.5 1 1.5 2 2.5 3 3.5 100 i out = 200ma v out (v) efficiency (%) 4.2v 5.0v 3.6v 65 70 75 80 85 90 95 100 0.51 1.52 2.533.5 i out = 200ma v in = 4.0v for v out = 3.3v, v in = 3.6v for all others. c in = 4.7f, c out = 10f, l x = 1h, t a = 25c unless otherwise noted. effi ciency vs. v out (t a = -40c) effi ciency vs. v out (t a = 25c) effi ciency vs. v out (t a = 85c)
SC195 6 v in = 4.0v for v out = 3.3v, v in = 3.6v for all others. c in = 4.7f, c out = 10f, l x = 1h, t a = 25c unless otherwise noted. frequency vs. temperature 1v 3.3v 2.8v 1.8v 3 3.2 3.4 3.6 3.8 4 -40 -20 0 20 40 60 80 100 temperature (c) frequency (mhz) load regulation (v out = 1.8v) 1.75 1.77 1.79 1.81 1.83 1.85 0 100 200 300 400 500 600 load current (ma) output voltage (v) -40 c 25c 85c -40 c 25c 1.75 1.77 1.79 1.81 1.83 1.85 2.5 3 3.5 4 4.5 5 5.5 v in (v) v out (v) 85c i out = 200ma line regulation (v out =1.8v) v in (v) -40c 85c 25c 82 83 84 85 86 87 88 89 90 2.5 3 3.5 4 4.5 5 5.5 6 efficiency (%) i out = 200ma effi ciency vs. v in (v out =1.8v) typical characteristics (continued)
SC195 7 typical characteristics (continued) light load switching v out = 1.8v time (400ns/div) v lx (2v/div) v out (50mv/div) i lx (200ma/div) light load switching v out = 1.0v time (400ns/div) v lx (2v/div) v out (50mv/div) i lx (200ma/div) light load switching v out = 2.8v time (400ns/div) v lx (2v/div) v out (50mv/div) i lx (200ma/div) light load switching v out = 3.3v time (400ns/div) v lx (2v/div) v out (50mv/div) i lx (200ma/div) heavy load switching v out = 1.0v time (200ns/div) i lx (200ma/div) v out (50mv/div) v lx (2.0v/div) heavy load switching v out = 1.8v time (200ns/div) i lx (200ma/div) v out (50mv/div) v lx (2v/div)
SC195 8 typical characteristics (continued) heavy load switching v out = 2.8v time (200ns/div) i lx (200ma/div) v out (50mv/div) v lx (2v/div) heavy load switching v out = 3.3v time (200ns/div) i lx (200ma/div) v out (50mv/div) v lx (2v/div) heavy load soft start time (40s/div) v out (1.0v/div) i in (200ma/div) i lx (500ma/div) light load soft start time (40s/div) v out (1.0v/div) i in (200ma/div) i lx (500ma/div) load transient response 10 to 80ma time (20s/div) i lx (200ma/div) v out (50mv/div) i load (50ma/div) load transient response 10 to 500ma time (20s/div) i lx (500ma/div) v out (100mv/div) i load (500ma/div) i load = 10ma i load = 500ma
SC195 9 typical characteristics (continued) load transient response 200 to 500ma time (20s/div) i lx (500ma/div) v out (100mv/div) i load (500ma/div) line transient response pwm time (20s/div) i lx (200ma/div) v out (100mv/div) v in 500mv/div) vid transient response pwm time (20s/div) v ctl2 (2.0v/div) v out (500mv/div) i lx (200ma/div) 1.2v to 1.8v transition vid transient response psave time (20s/div) v ctl2 (2.0v/div) v out (500mv/div) i lx (200ma/div) 1.2v to 1.8v transition line transient response psave time (40s/div) i lx (200ma/div) v out (100mv/div) v in (500mv/div) shutdown transient response time (20s/div) i lx (200ma/div) v out (2v/div) v in (2v/div) 3.5v to 4.0v transition on v in 3.5v to 4.0v transition on v in
SC195 10 pin descriptions pin pin name pin function 1ctl2 control bit 2 see table 1, page 2, for decoding. this pin has a weak pull-down resistor (> 1m ) in place at reset that is removed when ctl2 is pulled above the logic high threshold. 2ctl1 control bit 1 see table 1, page 2, for decoding. this pin has a weak pull-down resistor (> 1m ) in place at reset that is removed when ctl1 is pulled above the logic high threshold. 3ctl0 control bit 0 see table 1, page 2, for decoding. this pin has a weak pull-down resistor (> 1m ) in place at reset that is removed when ctl0 is pulled above the logic high threshold. 4 out output voltage sense pin output voltage regulation point (connection node of inductor and output capacitor). 5 gnd ground reference and power ground for the SC195. 6 lx switching output connect an inductor between this pin and the load to fi lter the pulsed output current. 7 in input power supply pin connect a bypass capacitor from this pin to gnd. 8ctl3 control bit 3 see table 1, page 2, for decoding. this pin has a weak pull-down resistor (> 1m ) in place at reset that is removed when ctl3 is pulled above the logic high threshold.
SC195 11 block diagram control logic plimit amp current amp nlimit amp osc & slope generator pwm comp error amp 500mv ref ctl2 ctl1 ctl0 out ctl3 gnd lx in voltage select 6 7 8 1 5 2 3 4 psave comp
SC195 12 general description the SC195 is a synchronous step-down pulse width modulated (pwm) dc-dc regulator utilizing a 3.5mhz fi xed-frequency voltage mode architecture. the device is designed to operate in fi xed-frequency pwm mode and enter power save (psave) mode utilizing pulse frequency modulation under light load conditions to maximize effi - ciency. the device requires only two capacitors and a single inductor to be implemented in most systems. the switching frequency has been chosen to minimize the size of the inductor and capacitors while maintaining high effi ciency. the output voltage is programmable, eliminat- ing the need for external programming resistors. loop compensation is also internal, eliminating the need for external components to control stability. programmable output voltage the SC195 has fi fteen fi xed output voltage levels which can be individually selected by programming the ctl control pins (ctl1-ctl4 see table 1 on page 2 for set- tings). the device is disabled whenever all four ctl pins are pulled low and enabled whenever at least one of the ctl pins is pulled high. this control approach eliminates the need for a dedicated enable pin. each ctl pin is inter- nally pulled down via 1m if v in is below 1.5v or if the voltage on the control pin is below the input high voltage. this ensures that the output is disabled when power is applied if there are no inputs to the ctl pins. each weak pull-down is disabled whenever its pin is pulled high and remains disabled until all ctl pins are pulled low. the output voltage can be set using diff erent approaches. if a static output voltage is required, the ctl pins can be tied to either in or gnd so that the desired voltage is set whenever power is applied at in. if enable control is required, each ctl pin can be tied to either gnd or to a microprocessor i/o line to create the desired control code whenever the control signal is forced high. this approach is equivalent to using the ctl pins collectively as a single enable pin. a third option is to connect each of the four ctl pins to individual microprocessor i/o lines. any of the 15 output voltages can be programmed using this approach. if only two output voltages are needed, the ctl pins can be combined in a way that will reduce the number of i/o lines to 1, 2, or 3, depending on the control code for each desired voltage. other ctl pins could be hard wired to gnd or in. this option allows dynamic voltage adjustment for systems that reduce the supply voltage when entering sleep states. note that applying all zeros to the ctl pins when changing the output volt- ages will temporarily disable the device, so it is important to avoid this combination when dynamically changing levels. pwm operation normal pwm operation occurs when the output load current exceeds the psave threshold. in this mode, the pmos high side switch is activated with the duty cycle required to produce the output voltage programmed by the ctl pins. an internal synchronous nmos rectifi er eliminates the need for an external schottky diode on the lx pin. as v in decreases, the duty cycle (percentage of time pmos is active) increases. as the input voltage approaches the programmed output voltage, the duty cycle approaches 100% (pmos always on) and the device enters a pass-through mode until the input voltage increases or the load decreases enough to allow pwm switching to resume. power save mode operation when the load current decreases below the psave threshold, pwm switching stops and the device auto- matically enters psave mode. this threshold varies depending on the input voltage and output voltage setting, optimizing effi ciency for all possible load currents - whether in pwm or psave mode. while in psave mode, output voltage regulation is controlled by a series of bursts in switching. during a burst, the inductor current is limited to a peak value which controls the on-time of the pmos switch. after reaching this peak, the pmos switch is disabled and the inductor current is forced to near 0ma. switching bursts continue until the output voltage climbs to v out +2.5% or until the psave current limit is reached. switching is then stopped to eliminate switching losses, enhancing overall effi ciency. switching resumes when the output voltage reaches the lower threshold of v out and continues until the upper threshold again is reached. note that the output voltage is regu- lated hysteretically while in psave mode between v out and v out + 2.5%. the period and duty cycle while in psave mode are solely determined by v in and v out until pwm applications information
SC195 13 mode resumes. this can result in the switching frequency being much lower than the pwm mode frequency. if the output load current increases enough to cause v out to decrease below the psave exit threshold (v out -2%), the device automatically exits psave and operates in continu- ous pwm mode. note that the psave high and low threshold levels are both set at or above v out to minimize undershoot when the SC195 exits psave. figure 1 illus- trates the transitions from pwm mode to psave mode and back to pwm mode. v out v out +2.5% v out -2% load demand ( i out ) burst off v lx time pwm mode at medium/high load psave mode at light load pwm mode at medium/high load psave exit figure 1 transitions between pwm and psave modes protection features the SC195 provides the following protection features: soft-start operation over-voltage protection current limit thermal shutdown under-voltage lockout soft-start the soft-start sequence is activated after a transition from an all zeros ctl code to a non-zero ctl code enables the part. soft-start is also activated by any overload event that causes the part to shutdown until the overload goes away. at start-up, the pmos current limit is stepped ? ? ? ? ? through four levels: 25%, 40%, 60%, and 100%. each step is maintained for 60s following an internal reference start up of 20s, resulting in a total nominal start-up period of 260s. if v out reaches 90% of the target within the fi rst 2 steps, the chip continues in psave mode at the end of soft-start; otherwise, it goes into pwm mode. note the v out ripple in psave mode can be larger than the ripple in pwm mode. over-voltage protection over-voltage protection is provided to ensure the output voltage does not rise to a level that could damage its load. when v out exceeds the regulation voltage by 15%, the pwm drive is disabled. switching does not resume until v out has fallen below the regulation voltage by 2%. current limit the SC195 switching stage is protected by a current limit function. if the output load exceeds the pmos current limit for 32 consecutive switching cycles, the device enters fold-back current limit mode and the output current is limited to approximately 150ma. under these conditions, the output voltage will be the product of i fb-lim and the load resistance. the load must fall below i fb-lim for the device to exit fold-back current limit mode. this func- tion makes the device capable of sustaining an indefi nite short circuit on its output under fault conditions. thermal shutdown the SC195 has a thermal shutdown feature to protect the device if the junction temperature exceeds 160c. during thermal shutdown, the pmos and nmos switches are both disabled, tri-stating the lx output. when the junc- tion temperature drops by the hysteresis value (20c), the device goes through the soft-start process and resumes normal operation. under-voltage lockout under-voltage lockout (uvlo) is enabled when the supply voltage drops below the uvlo threshold. this prevents the device from entering an ambiguous state in which regulation cannot be maintained. hysteresis of approximately 200mv is included to prevent chattering near the threshold. applications information (continued)
SC195 14 inductor selection the SC195 is designed to operate with a 1h inductor between the lx pin and the out pin. other values may lead to instability, malfunction, or out-of-specification performance. the specifi ed current levels for psave entry, psave exit, and current limit are dependent on the induc- tor value. the SC195 converter has internal loop compensation. the compensation is designed to work with a specifi c single- pole output filter corner frequency defined by the equation out c c l 2 1 f u s where, l = 1h and c out = 10f. when selecting output lter components, the lc product should not vary over a wide range. selection of smaller inductor and capacitor values will move the corner fre- quency, potentially impacting system stability. it is also important to consider the change in inductance with dc bias current when choosing an inductor. the inductor saturation current is speci ed as the current at which the inductance drops a speci c percentage from the nominal value (approximately 30%). except for short- circuit or other fault conditions, the peak current must always be less than the saturation current speci ed by the manufacturer. the peak current is the maximum load current plus one half of the inductor ripple current at the maximum input voltage. load and/or line transients can cause the peak current to exceed this level for short dura- tions. maintaining the peak current below the inductor saturation speci cation keeps the inductor ripple current and the output voltage ripple at acceptable levels. manufacturers often provide graphs of actual inductance and saturation characteristics versus applied inductor current. the saturation characteristics of the inductor can vary significantly with core temperature. core and ambient temperatures should be considered when exam- ining the core saturation characteristics. applications information (continued) when the inductor value has been determined, the dc resistance (dcr) must be examined. efficiency can be optimized by lowering the inductors dcr as much as pos- sible. low dcr in an inductor requires either more surface area for the increased wire diameter or fewer turns to reduce the length of the copper winding. fewer turns requires an inductor core with a larger cross-sectional area in order to maintain the same saturation characteristics. the inductor size must always be considered when exam- ining the inductor dcr to determine the best compromise between dcr and component area on a pcb. note that the ripple component of the inductor is a small percent- age of the dc load. ac losses in the inductor core and winding do not contribute significantly to the total losses. magnetic fi elds associated with the output inductor can interfere with nearby circuitry. this can be minimized by the use of low-noise shielded inductors which use the minimum gap possible to limit the distance that magnetic fi elds can radiate from the inductor. shielded inductors, however, typically have a higher dcr and are, therefore, less effi cient than a similar sized non-shielded inductor. final inductor selection depends on various design con- siderations such as effi ciency, emi, size, and cost. table 2 lists the manufacturers of recommended inductor options. the inductors with larger packages tend to provide better overall efficiency, while the smaller package inductors provide decent effi ciency with reduced footprint or height. the saturation current ratings and dc characteristics are also shown.
SC195 15 table 2 recommended inductors manufacturer part number l (h) dcr () saturation current (ma) l at 400ma (h) dimensions lxwxh (mm) murata lqm21pn1r0mc0 1.020% 0.19 800 0.75 2.0x1.25x0.55 murata lqm2hpn1r0mj0 1.020% 0.09 1500 0.95 2.5x2.0x1.1 murata lqm31pn1r0m00 1.020% 0.12 1200 0.95 3.2x1.6x0.85 taiyo yuden ckp25201r0m-t 1.020% 0.08 800 0.88 2.5x2.0x1.0 toko mdt2012-cr1r0n 1.030% 0.08 1350 1.00 2.0x1.25x1.0 fdk mipsz2012d1r0 1.030% 0.09 1100 1.00 2.0x1.25x1.0 fdk mipsu2520d1r0 1.030% 0.08 1300 0.78 2.5x2.0x0.5 fdk mipsa2520d1r0 1.330% 0.09 1200 1.20 2.5x2.0x1.2 taiyo yuden brc1608t1r0m 1.020% 0.18 850 0.90 1.6x0.8x0.8 c out selection the internal voltage loop compensation in the SC195 limits the minimum output capacitor value to 10f. this is due to its infl uence on the the loop crossover frequency, phase margin, and gain margin. increasing the output capacitor above this minimum value will reduce the cross- over frequency and provide greater phase margin. the output capacitor determines the output voltage ripple and contributes load current during large step load transitions. a capacitor between 10f and 22f will usually be adequate in stabilizing the output during large load transitions. capacitors with x7r or x5r ceramic dielectric are recom- mended for their low esr and superior temperature and voltage characteristics. y5v capacitors should not be used as their temperature coeffi cients make them unsuitable for this application. the output voltage droop due to a load transient is deter- mined by the capacitance of the ceramic output capacitor. the ceramic capacitor supplies the load current initially until the loop responds. within a few switching cycles the loop will respond and the inductor current will increase to match the required load. the output voltage droop during applications information (continued) the period prior to the loop responding can be related to the choice of output capacitor by the relationship f v i 3 c droop load out u ' u this equation determines the minimum value for the output capacitor with respect to load transient perfor- mance. once the inductor current increases its average value to the dc load current, the output voltage recovers. for example, for a step from 100ma to 500ma requiring less than 50mv droop, the output capacitance should be f 0 . 6 10 4 05 . 0 4 . 0 3 c 6 out p u u u the output capacitor rms current ripple may be calculated from the following equation. ? ? 1 ? u u u ) max ( in out ) max ( in out rms v f l v v v 3 2 1 i table 3 lists the manufacturers of recommended output capacitor options. table 3 recommended output capacitors manufacturer part nunber value (f) type rated voltage (vdc) dimensions lxwxh (mm) case size murata grm188r60j106me47d 1020% x5r 6.3 1.6x0.8x0.8 0603 murata grm21br60j106k 1010% x5r 6.3 2.0x1.25x1.25 0805 c in selection the SC195 input source current will appear as a dc supply current with a triangular ripple imposed on it. to prevent large input voltage ripple, a low esr ceramic capacitor is required. a minimum value of 4.7f should be used. it is important to consider the dc voltage coeffi cient charac- teristics when determining the actual required value. it should be noted that a 10f, 6.3v, x5r ceramic capacitor with 5v dc applied may exhibit a capacitance as low as 4.5f. the value of required input capacitance is estimated by determining the acceptable input ripple voltage and
SC195 16 calculating the minimum value required for c in from the equation f esr i v v v 1 v v c out in out in out in ? ? 1 ? ' ? ? 1 ? the input capacitor rms ripple current varies with the input and output voltage. the maximum input capacitor rms current is found from the equation ? ? 1 ? in out in out rms v v 1 v v i the input voltage ripple and rms current ripple are at maximum levels when the input voltage is twice the output voltage (50% duty cycle scenario). the input capacitor provides a low impedance loop for the edges of pulsed current drawn by the pmos switch. low esr/esl x5r ceramic capacitors are recommended for this function. to minimize stray inductance, the capaci- tor should be placed as closely as possible to the in and gnd pins of the SC195. table 4 lists the recommended input capacitor options from di erent manufacturers. table 4 recommended input capacitors manufacturer part nunber value (f) type rated voltage (vdc) dimensions lxwxh (mm) case size murata grm188r60j475k 4.710% x5r 6.3 1.6x0.8x0.8 0603 murata grm188r60j106k 1010% x5r 6.3 1.6x0.8x0.8 0603 taiyo yuden jmk107bj475ka 4.710% x5r 6.3 1.6x0.8x0.8 0603 pcb layout considerations the layout diagram in figure 2 shows a recommended pcb top-layer for the SC195 and supporting components. specifi ed layout rules must be followed since the layout is critical for achieving the performance specified in the electrical characteristics table. poor layout can degrade the performance of the dc-dc converter and can contrib- applications information (continued) ute to emi problems, ground bounce, and resistive voltage losses. poor regulation and instability can result. the following guidelines are recommended for designing a pcb layout: the input capacitor, c in should be placed as close to the vin and gnd pins as possible. this capacitor provides a low impedance loop for the pulsed currents present at the buck converters input. use short wide traces to connect as closely to the ic as possible. this will minimize emi and input voltage ripple by localizing the high frequency current pulses. keep the lx pin traces as short as possible to minimize pickup of high frequency switching edges to other parts of the circuit. c out and l x should be connected as close as possible between the lx and gnd pins, with a direct return to the gnd. use a ground plane referenced to the gnd pin. use several vias to connect to the component side ground to further reduce noise and interference on sensitive circuit nodes. route the output voltage feedback/sense path away from the inductor and lx node to minimize noise and magnetic interference. minimize the resistance from the out and gnd pins to the load. this will reduce errors in dc regulation due to voltage drops in the traces. ctl3 ctl2 ctl1 ctl0 l x c in c out SC195 4.8mm 3mm figure 2 recommended pcb layout 1. 2. 3. 4. 5.
SC195 17 .059 bsc 1.50 bsc notes: .004 8 .000 .020 - - (.006) 0.10 8 .024 .002 0.00 0.50 0.05 0.60 (0.1524) - - .004 0.10 1.50 bsc 0.40 bsc .016 bsc .014 0.35 .059 bsc a2 c seating plane e bxn lxn bbb c a b 1 2 n 0.20 0.25 0.17 0.40 0.30 0.16 0.12 a controlling dime nsions are in millimet ers (angles in degrees). 1. inches dimensions nom e bbb aaa a1 a2 dim n l e min d a millimeters max min max nom pin 1 indicator (laser mark) b .006 .008 .010 0.15 0.20 0.25 d a e b a1 aaa c outline drawing mlpq-ut8
semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 www.semtech.com contact information SC195 18 land pattern mlpq-ut8 inches dimensions p z x y c g dim millimeters r .004 0.10 1. controlling dimensions are in millimeters (angles in degrees). y x g z (g) (z) 2x (c) r p .030 .087 (.057) .028 0.75 2.20 (1.45) 0.70 0.20 0.40 .016 .008 this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 2.

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